Choosing a logic analyser
When choosing a logic analyzer, the primary considerations, in my mind are the following:
- Standalone device or USB? When dealing with traces from a logic analyzer, you are potentially dealing with large amounts of data. If the USB device streams the data to the computer (rather than storing it in an internal sample buffer), the amount of data you can capture is only limited by your computers memory. Additionally viewing the data on a large computer monitor is much easier that doing it on a pokey screen.
How many channels do you need? The basic RC2014 bus has 34 signals on it, so if you wanted to monitor the whole bus you’d need an LA with at least 34 channels! In most cases however it’s only necessary to look at the key Z80 signals, and that’s all the sigrok Z80 protocol decoder requires:
- Data bus (8)
- /WR In some situations you might want to also look at:
- Address bus (16) 11 channels is therefore a minimum, but obviously more is better :)
What sampling rate do you need? The RC2014 in it’s stock configuration runs at 7.3728MHz. When sampling a signal asynchronously, you need a sample rate 4x the frequency of the clocked signal so that no state transitions are missed. For a stock RC2014, that would mean needing 32MHz @ 11 channels. I’ve taken the alternative approach of clocking my RC2014 at half speed, meaning I only need to run the analyzer at 20MHz.
What is the software support from the manufacturer like, and is the device supported by sigrok?
Does it support using an external clock?
See https://sigrok.org/wiki/Downloads for details of installing it for your platform. Note on Arch sigrok-cli is in a separate AUR package on Arch Linux.
There may be additional steps for your particular logic analyzer. For the clone Saleae devices, it’s necessary to download one of their Logic releases and extract the FX2 firmware.
Connecting it to your RC2014
I constructed a small board that I could insert into the RC2014 backplane and connect the logic analyzer inputs to. This enabled quick insertion/ removal.
Recording the bus state
It is possible to acquire data from within the Pulseview application. I found that this was somewhat unstable (probably more due to my logic analyzer than anything else). If there is any problem aquiring the data, this isn’t fed back well to the user and the application can lock up. Instead, I found it was easier to use the
sigrok-cli application to capture the data and only use PulseView for viewing.
sigrok-cli --driver saleae-logic16 --config samplerate=20Mhz --channels 0=D0,1=D1,2=D2,3=D3,4=D4,5=D5,6=D6,7=D7,9=RD,10=WR,11=MREQ,12=CLK,13=M1,14=DATA_OE \ --samples 10M --output-file z80-fpga.sr
The bus state recording can then be viewed with Logicview. The Z80 protocol decoder is great to make sense of the data.